WoS İndeksli Yayınlar Koleksiyonu
Permanent URI for this collectionhttps://hdl.handle.net/20.500.12416/8653
Browse
Search Results
Article Signal-to-Noise Ratio Reduction in Non-Kolmogorov Jet Engine Exhaust Turbulence(IOP Publishing Ltd, 2026) Baykal, YahyaIn a medium experiencing non-Kolmogorov jet engine exhaust turbulence, signal-to-noise ratio (SNR) is evaluated. SNR is naturally degraded due to the presence of turbulence. The reduction in the SNR in non-Kolmogorov jet engine exhaust turbulence is calculated and presented with respect to the power law for various wireless optical communication link and turbulence parameters. The reduction in SNR is referenced to the SNR achieved in the link when there is no turbulence. SNR, being an important entity in determining the link performance, knowledge about the reduction in SNR will help the designers of wireless optical communication links, especially installed in airport environments where jet engine exhaust turbulence mostly occurs.Article Formal Verification for I2C Communication Protocol in Aerospace and Aviation Industries(Elsevier B.V., 2026) Berik, Merve; Baykal, YahyaThe aerospace industry comprises many safety-critical applications that involve a vast number of interacting subsystems. Reliable data communication between devices and components is therefore essential. In this context, Inter-Integrated Circuit (I2C) communication protocol is widely preferred due to its simplicity, flexibility, low power consumption, and reliability. However, issues such as data corruption, data loss, and increased latency may still occur and can lead to serious consequences in aviation, including safety risks, electronic malfunctions, air traffic management problems, and incorrect navigation information. To avoid such failures, the I2C RegisterTransfer Level (RTL) design must be both correctly implemented and rigorously verified. There are several verification methods for digital design verification. Among several digital design verification approaches, Formal Verification (FV) is one of the most precise and reliable methods for safety- critical systems, as it provides mathematical proofs of conformance to specified properties. In this work, an open-source, Yosys-based formal verification flow is applied to an open-source I2C master design using the SymbiYosys framework. The verification environment is developed in SystemVerilog with SystemVerilog Assertions, enabling the detection of design errors directly against the protocol requirements. By combining bounded model checking, cover analysis, and theorem-proving, the proposed flow systematically verifies all five finite-state-machine (FSM) states and nine transitions of the I2C master. The results demonstrate that formal verification can systematically ensure robust and fault-tolerant I2C operation for avionics applications.
